DVClub Silicon Valley - October 21, 2026, Dan Joyce Presenting

There is no cost, this FREE event includes, lunch, presentation and networking opportunities!

• 11:30am — Doors Open / Networking
• 12:00pm — Lunch / Presentation Dan Joyce
• 1:00pm — Networking

Presentation - Dan Joyce

"First Pass Silicon Success Requires These Ingredients"

Wall Street is rewarding Tech companies with sky high valuations because they are generating most of the earnings growth in the last 20 years. They are finally recognizing the contribution of well run Technological Development Teams with processes that work. First-pass silicon is critical to this equation. In 36 years of working on chip development in Design, Verification and Physical Design I have taped out 25 large ASICs and processors, with 24 first pass successes. I will give an overview of many key processes that I believe made the difference for these chips to make it to production without re-spin.

Included:

Design for Verification - Corner cases

Methodology Issues - XProp, Asynchronous Logic, Clocking, Power

Verification Processes Required to meet schedule

Gate Level Simulation - Finding Physical Design bugs that get through to silicon

Plus - How not to get locked into a EDA house

Dan Joyce worked at Tandem/Compaq/HP, Western Research Labs, Marvell, Oracle Labs, Samsung, SiFive, and Ericsson. Dan has taped out 25 large chips, performing Design, Verification and a little Implementation. Most of his career and his passion has been on Verification. The last 13 years he has focused on maximizing predictable, cost-effective first-pass success with Timing Gate-Level Simulation. Dan is now officially retired!

Register now and please share with your colleagues!