San Diego Joint Chapters - iMaps & ACers - Lunch & Learn with Trevor Yancey

Title: Wafer-Level Packaging Keeps Evolving: Insights from Recent Teardowns

Speaker bio: Trevor Yancey is a Senior Analyst with TechSearch International, Inc. He has more than 35 years of experience in the semiconductor industry, spanning hands-on chip analysis, packaging technology, and market and technology forecasting. Since joining TechSearch International in 2015, he has contributed to reports including Advanced Packaging Update, Flip Chip and WLP, and Quantifying the Impact of Heterogeneous Integration: Chiplets and SiP, and has built an extensive chip teardown and reverse engineering capability covering flagship smartphones, smartwatches, and other consumer devices selected for their advanced packaging content. Before TechSearch, he was vice president and co-founder of IC Insights, where he led research analysis of chip fabrication and packaging technology advancements and developed semiconductor market forecasts. He received his B.S. degree in Electrical Engineering from Arizona State University and is a member of IEEE, IMAPS, and SMTA.

The Details:

This presentation shares observations on wafer-level packaging drawn from recent teardowns, covering a range of consumer products including smartphones, wearables, gaming hardware, and consumer satellite communication equipment.

Four trends are discussed. First, WLP content per device is climbing generation-over-generation across product categories, as more functions migrate to wafer-level form factors. Second, minimum pitch continues to shrink, and non-standard pitches — departures from the long-standard 0.4 mm and 0.35 mm — are appearing more frequently, reflecting more aggressive package-level optimization. Third, molded WLP variants are showing up in a wider range of applications, with specific examples pulled from recent devices. Fourth, fan-out WLP and panel-level fan-out continue to evolve at the high end, most visibly in Google's Tensor G5, which moved from Samsung's panel fan-out platform to TSMC's InFO — a transition that underscores the ongoing competition between fan-out platforms for leading-edge sockets.

Each trend is illustrated with specific teardown examples to show where WLP stands today.

Date: 05/13/2026

Time: 11:45am- 1:00pm

Location:

AI Technology (Formerly EMD Performance Materials)

6555 Nancy Ridge Dr.

San Diego, CA 92131

• $25 members / $30 non-members / Free for students with ID (Includes lunch)
• Please invite your friends and students - we always welcome new faces

We look forward to seeing you there!

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