Maximize RISC-V Performance with Custom Design
About this Event
Maximize RISC-V Performance with Custom Design
Join us in person for an exciting opportunity to dive deep into RISC-V performance optimization! Whether you're a developer, engineer, or just a tech enthusiast, this event will show you how to push the boundaries with custom designs that make your RISC-V projects run faster and smarter. Don’t miss out on hands-on experiences and networking with like-minded innovators!
Agenda
🕑: 10:00 AM - 10:30 AM
Check-In
🕑: 10:30 AM - 10:40 AM
Andes: your Commercial-Grade RISC-V Processor IP Partner
Host: Emerson Hsiao
Info: Emerson Hsiao, President of Andes Technology USA, will welcome attendees and provide a brief overview of Andes Technology, including RISC-V market trends, ecosystem collaboration, Andes’ processor IP portfolio and solutions, and customer success stories.
🕑: 10:40 AM - 11:10 AM
Accelerating RISC-V with Andes Custom Extensions (ACE) (TBD)
Host: Darren Jones
🕑: 11:10 AM - 11:40 AM
Breaking the Memory Wall: Improving CPU Performance Beyond Compute
Host: Mia Chang
Info: Mia Chang will explore how modern CPU performance is increasingly limited by memory access rather than compute capability. She will discuss key memory bottlenecks and practical approaches to improving system performance through better CPU and memory architecture.
🕑: 11:40 AM - 12:10 PM
DGEMM Optimization & RISC-V Vector Performance
Host: Trevor Cooper
Info: Trevor Cooper will explore DGEMM optimization on RISC-V, highlighting how the RISC-V Vector (RVV) extension can improve floating-point performance. The session will cover key optimization techniques, performance considerations, and practical approaches to maximizing vector processing efficiency.
🕑: 12:10 PM - 02:00 PM
Lunch and Networking
Info: Enjoy a complimentary lunch while connecting with Andes experts, speakers, and fellow RISC-V professionals.
Where is it happening?
Event Location & Nearby Stays:
USD 0.00
